The present invention relates to chip stacks, and more specifically, to 3D chip stacks with electrically insulating walls between microbumps.
In 3D chip stacks, chips such as integrated circuits are layered on top of one another in a three-dimensional stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a given two-dimensional area with an increased amount of electrical communications between them. Since there is no thermal expansion mismatch between silicon chips, finer pitch (</=100 microns) electrical interconnects, such as microbumps with a density of ten thousand or more connections per square centimeter, can be used. However, such 3D chip stacks are more difficult to adequately cool then a planar array of individual chips.
Recently, it has been seen that the thermal resistance of a microbump joining layer between chips in a 3D chip stack can limit allowable power distributions and stack heights. Moreover, in conventional flip-chip bonding, a size of a microbump area is limited to a given percentage of a total size of a fully populated array. This design rule is used to prevent a given microbump from “bridging” between adjacent pads. Thus, in an effort to prevent bridging, it is often necessary to limit a size of a microbumps area in a microbump array.
For example, in a conventional flip-chip bonding process a pick and place tool may be used to place the chip face down on a substrate where the chip contains solder balls on about 200 micron pitch, for example, controlled collapse chip connections (C4s), and the substrate contains matching pads, and the combination is then passed through a reflow furnace to join the chip to the substrate by melting the solder. The surface tension of the solder in the molten state serves to “self-align” the chip to the substrate, assuming that the solder balls are placed on the appropriate pads. To avoid having solder “bridging” between adjacent pads, or a C4 solder ball contact multiple pads on the substrate, the solder ball diameter usually does not exceed half of the pitch between solder pads. For a square array, this means that the solder area is limited to about 20% of the total joint area.
These limitations often lead to limits in the allowable power distributions and stack heights in 3D chip stacks due to the thermal resistance of the microbump joining layer(s).